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Hyper-V platform remains greyed out in control panel

    Question

  • It appears I meet the pre-reqs but when I go to enable Hyper-V via the control panel the Hyper-V platform option is greyed out.

    I have Windows 8 Pro 64-bit and run both coreinfo and the AMD tool (amdvhyperv) which suggest I'm set to go.

    Not sure what else to check.

    AMD Phenom(tm) 8450 Triple-Core Processor
    AMD64 Family 16 Model 2 Stepping 3, AuthenticAMD
    HYPERVISOR - Hypervisor is present
    SVM * Supports AMD hardware-assisted virtualization
    NP * Supports AMD nested page tables (SLAT)


    AMD Phenom(tm) 8450 Triple-Core Processor
    AMD64 Family 16 Model 2 Stepping 3, AuthenticAMD
    HTT             *       Multicore
    HYPERVISOR      -       Hypervisor is present
    VMX             -       Supports Intel hardware-assisted virtualization
    SVM             *       Supports AMD hardware-assisted virtualization
    EM64T           *       Supports 64-bit mode

    SMX             -       Supports Intel trusted execution
    SKINIT          -       Supports AMD SKINIT

    NX              *       Supports no-execute page protection
    SMEP            -       Supports Supervisor Mode Execution Prevention
    PAGE1GB         *       Supports 1 GB large pages
    PAE             *       Supports > 32-bit physical addresses
    PAT             *       Supports Page Attribute Table
    PSE             *       Supports 4 MB pages
    PSE36           *       Supports > 32-bit address 4 MB pages
    PGE             *       Supports global bit in page tables
    SS              -       Supports bus snooping for cache operations
    VME             *       Supports Virtual-8086 mode
    RDWRFSGSBASE    -       Supports direct GS/FS base access

    FPU             *       Implements i387 floating point instructions
    MMX             *       Supports MMX instruction set
    MMXEXT          *       Implements AMD MMX extensions
    3DNOW           *       Supports 3DNow! instructions
    3DNOWEXT        *       Supports 3DNow! extension instructions
    SSE             *       Supports Streaming SIMD Extensions
    SSE2            *       Supports Streaming SIMD Extensions 2
    SSE3            *       Supports Streaming SIMD Extensions 3
    SSSE3           -       Supports Supplemental SIMD Extensions 3
    SSE4.1          -       Supports Streaming SIMD Extensions 4.1
    SSE4.2          -       Supports Streaming SIMD Extensions 4.2

    AES             -       Supports AES extensions
    AVX             -       Supports AVX intruction extensions
    FMA             -       Supports FMA extensions using YMM state
    MSR             *       Implements RDMSR/WRMSR instructions
    MTRR            *       Supports Memory Type Range Registers
    XSAVE           -       Supports XSAVE/XRSTOR instructions
    OSXSAVE         -       Supports XSETBV/XGETBV instructions
    RDRAND          -       Supports RDRAND instruction

    CMOV            *       Supports CMOVcc instruction
    CLFSH           *       Supports CLFLUSH instruction
    CX8             *       Supports compare and exchange 8-byte instructions
    CX16            *       Supports CMPXCHG16B instruction
    DCA             -       Supports prefetch from memory-mapped device
    F16C            -       Supports half-precision instruction
    FXSR            *       Supports FXSAVE/FXSTOR instructions
    FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
    MONITOR         *       Supports MONITOR and MWAIT instructions
    MOVBE           -       Supports MOVBE instruction
    PCLULDQ         -       Supports PCLMULDQ instruction
    POPCNT          *       Supports POPCNT instruction
    SEP             *       Supports fast system call instructions
    LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode

    DE              *       Supports I/O breakpoints including CR4.DE
    DTES64          -       Can write history of 64-bit branch addresses
    DS              -       Implements memory-resident debug buffer
    DS-CPL          -       Supports Debug Store feature with CPL
    PCID            -       Supports PCIDs and settable CR4.PCIDE
    PDCM            -       Supports Performance Capabilities MSR
    RDTSCP          *       Supports RDTSCP instruction
    TSC             *       Supports RDTSC instruction
    TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
    TSC-INVARIANT   *       TSC runs at constant rate
    xTPR            -       Supports disabling task priority messages

    EIST            -       Supports Enhanced Intel Speedstep
    ACPI            -       Implements MSR for power management
    TM              -       Implements thermal monitor circuitry
    TM2             -       Implements Thermal Monitor 2 control
    APIC            *       Implements software-accessible local APIC
    x2APIC          -       Supports x2APIC

    CNXT-ID         -       L1 data cache mode adaptive or BIOS

    MCE             *       Supports Machine Check, INT18 and CR4.MCE
    MCA             *       Implements Machine Check Architecture
    PBE             -       Supports use of FERR#/PBE# pin

    PSN             -       Implements 96-bit processor serial number

    PREFETCHW       *       Supports PREFETCHW instruction

    Logical to Physical Processor Map:
    *--  Physical Processor 0
    -*-  Physical Processor 1
    --*  Physical Processor 2

    Logical Processor to Socket Map:
    ***  Socket 0

    Logical Processor to NUMA Node Map:
    ***  NUMA Node 0

    Logical Processor to Cache Map:
    *--  Data Cache          0, Level 1,   64 KB, Assoc   2, LineSize  64
    *--  Instruction Cache   0, Level 1,   64 KB, Assoc   2, LineSize  64
    *--  Unified Cache       0, Level 2,  512 KB, Assoc  16, LineSize  64
    ***  Unified Cache       1, Level 3,    2 MB, Assoc   1, LineSize  64
    -*-  Data Cache          1, Level 1,   64 KB, Assoc   2, LineSize  64
    -*-  Instruction Cache   1, Level 1,   64 KB, Assoc   2, LineSize  64
    -*-  Unified Cache       2, Level 2,  512 KB, Assoc  16, LineSize  64
    --*  Data Cache          2, Level 1,   64 KB, Assoc   2, LineSize  64
    --*  Instruction Cache   2, Level 1,   64 KB, Assoc   2, LineSize  64
    --*  Unified Cache       3, Level 2,  512 KB, Assoc  16, LineSize  64

    Tuesday, October 30, 2012 12:49 PM

Answers

All replies

  • Same problem for me:

    I ran Coreinfo.exe -v and all 3 are supported.

    Windows 8 Pro (upgraded from Windows 8 Home, maybe the issue?)


    Regards

    • Proposed as answer by hedayah Friday, March 14, 2014 7:34 PM
    Wednesday, October 31, 2012 5:02 PM
  • You have to be running the 64-bit version of Windows 8 Pro to run the
    Hyper-V feature. (and not in a VM)
     
     
     

    Bob Comer - Microsoft MVP Virtual Machine
    Wednesday, October 31, 2012 6:52 PM
  • Same problem for me:

    I ran Coreinfo.exe -v and all 3 are supported.

    Windows 8 Pro (upgraded from Windows 8 Home, maybe the issue?)



    no, you have a different issue. Core2Duo DOESN'T Support SLAT!

    The "-" in CoreInfo means NO support for this feature.

    @thecampbells

    try to activate Hyper-V via DISM and also update the BIOS.


    "A programmer is just a tool which converts caffeine into code"

    Wednesday, October 31, 2012 10:19 PM
  • Oh thanks. Well, time for new hardware I guess...

    Regards

    Wednesday, October 31, 2012 11:05 PM
  • Install Hyper-V on Windows 8 must meet:

    1 64Bit operation

    2 CPU should support Second Level Address Translation (SLAT),

    http://social.technet.microsoft.com/wiki/contents/articles/1401.hyper-v-list-of-slat-capable-cpus-for-hosts.aspx

    3 At least 4G Ram

    Furthermore, update BIOS and enable virtualization.

    Regards,

    Leo   Huang


    Leo Huang

    TechNet Community Support

    Thursday, November 01, 2012 6:11 AM
    Moderator
  • I have checked all the required information mentioned in this topic.

    Sony Vaio T Series Running 64-bit Windows 8 Pro

    Intel I7 w/ 8GB

    I have set the Virtualization to Enables in the BIOS,

    I have upgraded to Windows 8 Pro using a pro pack upgrade

    Add Features still shows Hyper-V Platform greyed out.

    What is the secret handshake between Windows and the BIOS that's not been done?

    Thanks - Jonathan

    Sunday, March 17, 2013 9:43 PM
  • Have you used CoreInfo to see if the Windows detects all features?

    "A programmer is just a tool which converts caffeine into code"

    Monday, March 18, 2013 5:39 AM
  • Unfortunately, Sony has always been notorious for not allowing hardware virtualization on their systems.

    After you enabled virtualization in the BIOS did you do a cold start?  Ideally, pull the power and battery and wait 10-30 seconds and then start the system.  This will force the changes in the BIOS to be reloaded.

    Monday, March 18, 2013 5:08 PM
  • I'll try the cold boot and let you know what happens..  Thanks!
    Monday, March 18, 2013 8:51 PM
  • Still no joy.  BIOS says it's enabled, SystemInfo says it's not.

    CoreInfo.exe says this:

    Coreinfo v3.2 - Dump information on system CPU and memory topology
    Copyright (C) 2008-2012 Mark Russinovich
    Sysinternals - www.sysinternals.com

    Intel(R) Core(TM) i7-3537U CPU @ 2.00GHz
    Intel64 Family 6 Model 58 Stepping 9, GenuineIntel
    HTT             *       Hyperthreading enabled
    HYPERVISOR      -       Hypervisor is present
    VMX             *       Supports Intel hardware-assisted virtualization
    SVM             -       Supports AMD hardware-assisted virtualization
    EM64T           *       Supports 64-bit mode

    SMX             -       Supports Intel trusted execution
    SKINIT          -       Supports AMD SKINIT

    NX              *       Supports no-execute page protection
    SMEP            *       Supports Supervisor Mode Execution Prevention
    SMAP            -       Supports Supervisor Mode Access Prevention
    PAGE1GB         -       Supports 1 GB large pages
    PAE             *       Supports > 32-bit physical addresses
    PAT             *       Supports Page Attribute Table
    PSE             *       Supports 4 MB pages
    PSE36           *       Supports > 32-bit address 4 MB pages
    PGE             *       Supports global bit in page tables
    SS              *       Supports bus snooping for cache operations
    VME             *       Supports Virtual-8086 mode
    RDWRFSGSBASE    *       Supports direct GS/FS base access

    FPU             *       Implements i387 floating point instructions
    MMX             *       Supports MMX instruction set
    MMXEXT          -       Implements AMD MMX extensions
    3DNOW           -       Supports 3DNow! instructions
    3DNOWEXT        -       Supports 3DNow! extension instructions
    SSE             *       Supports Streaming SIMD Extensions
    SSE2            *       Supports Streaming SIMD Extensions 2
    SSE3            *       Supports Streaming SIMD Extensions 3
    SSSE3           *       Supports Supplemental SIMD Extensions 3
    SSE4.1          *       Supports Streaming SIMD Extensions 4.1
    SSE4.2          *       Supports Streaming SIMD Extensions 4.2

    AES             *       Supports AES extensions
    AVX             *       Supports AVX intruction extensions
    FMA             -       Supports FMA extensions using YMM state
    MSR             *       Implements RDMSR/WRMSR instructions
    MTRR            *       Supports Memory Type Range Registers
    XSAVE           *       Supports XSAVE/XRSTOR instructions
    OSXSAVE         *       Supports XSETBV/XGETBV instructions
    RDRAND          *       Supports RDRAND instruction
    RDSEED          -       Supports RDSEED instruction

    CMOV            *       Supports CMOVcc instruction
    CLFSH           *       Supports CLFLUSH instruction
    CX8             *       Supports compare and exchange 8-byte instructions
    CX16            *       Supports CMPXCHG16B instruction
    BMI1            -       Supports bit manipulation extensions 1
    BMI2            -       Supports bit maniuplation extensions 2
    ADX             -       Supports ADCX/ADOX instructions
    DCA             -       Supports prefetch from memory-mapped device
    F16C            *       Supports half-precision instruction
    FXSR            *       Supports FXSAVE/FXSTOR instructions
    FFXSR           -       Supports optimized FXSAVE/FSRSTOR instruction
    MONITOR         *       Supports MONITOR and MWAIT instructions
    MOVBE           -       Supports MOVBE instruction
    ERMSB           *       Supports Enhanced REP MOVSB/STOSB
    PCLULDQ         *       Supports PCLMULDQ instruction
    POPCNT          *       Supports POPCNT instruction
    SEP             *       Supports fast system call instructions
    LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
    HLE             -       Supports Hardware Lock Elision instructions
    RTM             -       Supports Restricted Transactional Memory instructions

    DE              *       Supports I/O breakpoints including CR4.DE
    DTES64          *       Can write history of 64-bit branch addresses
    DS              *       Implements memory-resident debug buffer
    DS-CPL          *       Supports Debug Store feature with CPL
    PCID            *       Supports PCIDs and settable CR4.PCIDE
    INVPCID         -       Supports INVPCID instruction
    PDCM            *       Supports Performance Capabilities MSR
    RDTSCP          *       Supports RDTSCP instruction
    TSC             *       Supports RDTSC instruction
    TSC-DEADLINE    *       Local APIC supports one-shot deadline timer
    TSC-INVARIANT   *       TSC runs at constant rate
    xTPR            *       Supports disabling task priority messages

    EIST            *       Supports Enhanced Intel Speedstep
    ACPI            *       Implements MSR for power management
    TM              *       Implements thermal monitor circuitry
    TM2             *       Implements Thermal Monitor 2 control
    APIC            *       Implements software-accessible local APIC
    x2APIC          *       Supports x2APIC

    CNXT-ID         -       L1 data cache mode adaptive or BIOS

    MCE             *       Supports Machine Check, INT18 and CR4.MCE
    MCA             *       Implements Machine Check Architecture
    PBE             *       Supports use of FERR#/PBE# pin

    PSN             -       Implements 96-bit processor serial number

    PREFETCHW       *       Supports PREFETCHW instruction

    Logical to Physical Processor Map:
    **--  Physical Processor 0 (Hyperthreaded)
    --**  Physical Processor 1 (Hyperthreaded)

    Logical Processor to Socket Map:
    ****  Socket 0

    Logical Processor to NUMA Node Map:
    ****  NUMA Node 0

    Logical Processor to Cache Map:
    **--  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
    **--  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
    **--  Unified Cache       0, Level 2,  256 KB, Assoc   8, LineSize  64
    ****  Unified Cache       1, Level 3,    4 MB, Assoc  16, LineSize  64
    --**  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
    --**  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
    --**  Unified Cache       2, Level 2,  256 KB, Assoc   8, LineSize  64

    Logical Processor to Group Map:
    ****  Group 0

    Monday, March 18, 2013 9:21 PM
  • Well, here's some news for your contemplation.

    On the Sony community site, it was said by "mattblackcube" that:

    "I then remembered that Windows 8 doesn't do a traditional "shut down", but some hybrid state. In other words, when we get out of the BIOS settings change, Windows hasn't rebooted and hence hasn't got the settings from the BIOS. The solution is simple. Once you're back in Windows after the BIOS setting change, do not SHUT DOWN Instead, choose the RESTART option. Once Windows reboots properly, you'll see that the hyper-v option is no longer greyed out. Hope this helps"

    It did.  Once I used Restart, instead of a shutdown, the Hyper-V Platform option was available and successfully activated/installed.  

    Odd to read that tidbit on Sony's site but not here..

    • Proposed as answer by jdharley1 Tuesday, March 19, 2013 12:16 PM
    Tuesday, March 19, 2013 12:16 PM
  • >Odd to read that tidbit on Sony's site but not here..
     
    Not really, nobody ran into it before or didn't talk about it.  Now we
    know, so thanks!
     
     

    Bob Comer - Microsoft MVP Virtual Machine
    Tuesday, March 19, 2013 12:40 PM
  • I am having the same issue. Hyper-V Platform is greyed out.

    Windows 2008 R2 did run hyperv on this hardware.

    I am trying to attempt to replicate a customer issue with our product in the Win8.1 Pro version.

    Coreinfo -v reports:


    Intel(R) Xeon(TM) CPU 3.20GHz
    Intel64 Family 15 Model 6 Stepping 4, GenuineIntel
    HYPERVISOR - Hypervisor is present
    VMX        * Supports Intel hardware-assisted virtualization
    EPT        - Supports Intel extended page tables (SLAT)

    Coreinfo reports:

    Intel(R) Xeon(TM) CPU 3.20GHz
    Intel64 Family 15 Model 6 Stepping 4, GenuineIntel
    HTT        * Hyperthreading enabled
    HYPERVISOR - Hypervisor is present
    VMX        * Supports Intel hardware-assisted virtualization
    SVM        - Supports AMD hardware-assisted virtualization
    EM64T      * Supports 64-bit mode

    SMX        - Supports Intel trusted execution
    SKINIT     - Supports AMD SKINIT

    NX         * Supports no-execute page protection
    SMEP       - Supports Supervisor Mode Execution Prevention
    SMAP       - Supports Supervisor Mode Access Prevention
    PAGE1GB    - Supports 1 GB large pages
    PAE        * Supports > 32-bit physical addresses
    PAT        * Supports Page Attribute Table
    PSE        * Supports 4 MB pages
    PSE36      * Supports > 32-bit address 4 MB pages
    PGE        * Supports global bit in page tables
    SS         * Supports bus snooping for cache operations
    VME        * Supports Virtual-8086 mode
    RDWRFSGSBASE - Supports direct GS/FS base access

    FPU        * Implements i387 floating point instructions
    MMX        * Supports MMX instruction set
    MMXEXT     - Implements AMD MMX extensions
    3DNOW      - Supports 3DNow! instructions
    3DNOWEXT   - Supports 3DNow! extension instructions
    SSE        * Supports Streaming SIMD Extensions
    SSE2       * Supports Streaming SIMD Extensions 2
    SSE3       * Supports Streaming SIMD Extensions 3
    SSSE3      - Supports Supplemental SIMD Extensions 3
    SSE4a      - Supports Sreaming SIMDR Extensions 4a
    SSE4.1     - Supports Streaming SIMD Extensions 4.1
    SSE4.2     - Supports Streaming SIMD Extensions 4.2

    AES        - Supports AES extensions
    AVX        - Supports AVX intruction extensions
    FMA        - Supports FMA extensions using YMM state
    MSR        * Implements RDMSR/WRMSR instructions
    MTRR       * Supports Memory Type Range Registers
    XSAVE      - Supports XSAVE/XRSTOR instructions
    OSXSAVE    - Supports XSETBV/XGETBV instructions
    RDRAND     - Supports RDRAND instruction
    RDSEED     - Supports RDSEED instruction

    CMOV       * Supports CMOVcc instruction
    CLFSH      * Supports CLFLUSH instruction
    CX8        * Supports compare and exchange 8-byte instructions
    CX16       * Supports CMPXCHG16B instruction
    BMI1       - Supports bit manipulation extensions 1
    BMI2       - Supports bit manipulation extensions 2
    ADX        - Supports ADCX/ADOX instructions
    DCA        - Supports prefetch from memory-mapped device
    F16C       - Supports half-precision instruction
    FXSR       * Supports FXSAVE/FXSTOR instructions
    FFXSR      - Supports optimized FXSAVE/FSRSTOR instruction
    MONITOR    * Supports MONITOR and MWAIT instructions
    MOVBE      - Supports MOVBE instruction
    ERMSB      - Supports Enhanced REP MOVSB/STOSB
    PCLULDQ    - Supports PCLMULDQ instruction
    POPCNT     - Supports POPCNT instruction
    LZCNT      - Supports LZCNT instruction
    SEP        * Supports fast system call instructions
    LAHF-SAHF  * Supports LAHF/SAHF instructions in 64-bit mode
    HLE        - Supports Hardware Lock Elision instructions
    RTM        - Supports Restricted Transactional Memory instructions

    DE         * Supports I/O breakpoints including CR4.DE
    DTES64     * Can write history of 64-bit branch addresses
    DS         * Implements memory-resident debug buffer
    DS-CPL     * Supports Debug Store feature with CPL
    PCID       - Supports PCIDs and settable CR4.PCIDE
    INVPCID    - Supports INVPCID instruction
    PDCM       * Supports Performance Capabilities MSR
    RDTSCP     - Supports RDTSCP instruction
    TSC        * Supports RDTSC instruction
    TSC-DEADLINE - Local APIC supports one-shot deadline timer
    TSC-INVARIANT - TSC runs at constant rate
    xTPR       * Supports disabling task priority messages

    EIST       - Supports Enhanced Intel Speedstep
    ACPI       * Implements MSR for power management
    TM         * Implements thermal monitor circuitry
    TM2        - Implements Thermal Monitor 2 control
    APIC       * Implements software-accessible local APIC
    x2APIC     - Supports x2APIC

    CNXT-ID    * L1 data cache mode adaptive or BIOS

    MCE        * Supports Machine Check, INT18 and CR4.MCE
    MCA        * Implements Machine Check Architecture
    PBE        * Supports use of FERR#/PBE# pin

    PSN        - Implements 96-bit processor serial number

    PREFETCHW  * Supports PREFETCHW instruction

    Maximum implemented CPUID leaves: 00000006 (Basic), 80000008 (Extended).

    Logical to Physical Processor Map:
    **------  Physical Processor 0 (Hyperthreaded)
    --**----  Physical Processor 1 (Hyperthreaded)
    ----**--  Physical Processor 2 (Hyperthreaded)
    ------**  Physical Processor 3 (Hyperthreaded)

    Logical Processor to Socket Map:
    ****----  Socket 0
    ----****  Socket 1

    Logical Processor to NUMA Node Map:
    ********  NUMA Node 0

    Logical Processor to Cache Map:
    **------  Data Cache          0, Level 1,   16 KB, Assoc   8, LineSize  64
    **------  Unified Cache       0, Level 2,    2 MB, Assoc   8, LineSize 128
    --**----  Data Cache          1, Level 1,   16 KB, Assoc   8, LineSize  64
    --**----  Unified Cache       1, Level 2,    2 MB, Assoc   8, LineSize 128
    ----**--  Data Cache          2, Level 1,   16 KB, Assoc   8, LineSize  64
    ----**--  Unified Cache       2, Level 2,    2 MB, Assoc   8, LineSize 128
    ------**  Data Cache          3, Level 1,   16 KB, Assoc   8, LineSize  64
    ------**  Unified Cache       3, Level 2,    2 MB, Assoc   8, LineSize 128

    Logical Processor to Group Map:
    ********  Group 0

    Monday, March 10, 2014 7:26 PM
  • Windows 8 Hyper-V requires SLAT or as Intel calls it EPT.

    You don't have it, from your results:  "EPT   - Supports Intel extended page tables (SLAT)"

    The server versions of Hyper-V don't require it, only Win8.  It allows for a better user experience with graphics, etc.

    There is no way to disable this requirement with Windows 8.


    • Edited by Steve JainMVP Monday, March 10, 2014 8:07 PM clarifictation
    Monday, March 10, 2014 8:06 PM
  • So the '-' is indicating that it is not there and I would have had to see an '*' in order for it to be available.

    Thanks for your help.

    Monday, March 10, 2014 9:30 PM
  • means not present, the '*' means present/supported

    You'd want to see this from the "coreinfo -v" command

    HYPERVISOR      -       Hypervisor is present
    VMX             *       Supports Intel hardware-assisted virtualization
    EPT             *       Supports Intel extended page tables (SLAT)

    -v just dumps the info relevant to virtualization

    Monday, March 10, 2014 11:13 PM
  • I'm having the same issue even tho my PC is a

    Processor

    Intel (R) Core (TM) i5-4300U CPU 1.9GHz 2.49GHz

    64 Bit processor

    Windows 8.1 Pro

    4GB of ram

    Saturday, August 23, 2014 9:01 PM
  • I'm having the same issue even tho my PC is a

    Processor

    Intel (R) Core (TM) i5-4300U CPU 1.9GHz 2.49GHz

    64 Bit processor

    Windows 8.1 Pro

    4GB of ram

    Ideally, can you start a new thread for your issue?  Also, include your coreinfo -v results.

    Tuesday, August 26, 2014 5:40 PM